AMD Phenom Errarta 298 - Important or Hype?
When AMD was briefing the media about Phenom at their launch event they mentioned that a fix was in the works for one of the hundreds of erratums that the Phenom processor has. All processors have glitches and they are documented and given a erratum number. As time goes on many of these get fixed with BIOS updates and whole new CPU steppings. This is normal and the way AMD and Intel have developed and updated processors for decades. The erratum that was in the fix dealt with the Translation lookaside buffers (TLB) on the new L3 cache fond only on Phenom processors. Translation lookaside buffers help the processor map virtual addresses to physical addresses. They hold the most recently used page mapping information in fast, chip-resident memory to speed up address translation. When a TLB miss occurs, page mapping information can be lost if it is not found in the L1 or L2 caches. For some reason AMD didn't fully expose how minor/major the erratum was, so when Scott over at the Tech Report wrote about huge performance loses when the TLB erratum was fixed many in the industry freaked out. At the time of his article the BIOS fix for the TLB erratum was automatically enabled in the BIOS and was not able to be turned off. A couple weeks ago we got our hands on OverDrive 2.0.12 and found by using the Turbo button the TLB patch can be disabled. AMD just this week released OverDrive 2.0.13 beta, which adds more features but still lacks 64-Bit driver signing. That means if you are running 64-bit Vista for example you have to disable driver signing by hitting F8 while windows is booting, change the setting and then let Windows Vista 64-bit fully load.
